(a) Field of the Invention
The present invention relates to a phase lock loop and, more particularly, to a phase lock loop having a reduced synchronization transfer period for use as a reference frequency signal source in a microprocessor, a communication system and the like.
(b) Description of the Related Art
A phase lock loop (PLL) is widely used as a generator for a reference frequency signal such as a clock signal in a microprocessor and a local oscillating signal in a communication system and the like.
FIG. 1 shows a first conventional phase lock loop in a block diagram. The first conventional phase lock loop includes a phase comparator 1, a charge pump circuit 2, a low-pass filter 3, a voltage controlled oscillator (VCO) 4 and a frequency divider 5.
Referring to FIG. 2A showing an example of the configuration of the VCO 4, the VCO 4 is implemented by a variable delay circuit 40 including cascaded N variable delay gates D1 to DN, in which each of transmission delays of the delay gates D1 to DN is varied based on the voltage level of the control signal CC. The output of the final stage variable delay gate DN is connected to the input of the first stage variable delay gates D1 to form a loop for oscillation.
Referring to FIG. 2B showing a configuration of one of the variable delay gates; D1 to DN, the variable delay gate is comprised of a CMOS inverter including a PMOS transistor P41 and an NMOS transistor N41, a transistor N42 having a drain connected to the output of the CMOS inverter, a source connected to one of the terminals of a capacitor C41 having the other of the terminals grounded and a gate supplied with the control signal CC, wherein the variable delay gate varies the delay thereof by controlling the load capacitance of the CMOS inverter based on the voltage level of the control signal CC.
Referring back to FIG. 1, in operation, the phase comparator 1 supplies the charge pump circuit 2 with a phase difference signals PDA and PDB based on a phase difference between the external reference clock CKR and the output SD of the frequency divider 5. The charge pump circuit 2 converts the phase difference signals PDA and PDB Into an error signal CD, which exhibits a level change proportional to the phase difference between the reference clock CKR and the divided signal SD. The error signal CD is smoothed by the low-pass filter 3 to generate a control signal CC. The VC0 4 generates an output clock CK0 having an oscillation frequency which is controlled based on the voltage level of the control signal CC. The frequency divider 5 generates a divided signal SD by dividing the output clock CK0 at a predetermined dividing ratio M, thereby supplying the output thereof to the phase comparator 1.
When the entire circuit is a steady state of the operation, i.e., a synchronous state after the synchronization transfer period, the frequencies and phases of the reference clock CKR and the divided signal SD coincide with each other. Accordingly, the output clock CK0 supplied from the VCO 4 corresponds to a signal obtained by multiplication of the reference clock CKR by the dividing ratio M.
The synchronization transfer period mentioned above corresponds to a transient period required for transferring the phase lock loop into the steady state for synchronization and is determined by a sum of a pull-in period, which is referred to as a frequency synchronization period, and a lock-in period, which is referred to as a phase synchronization period. In order to reduce the synchronization transfer period. One method that has been suggested is to increase the loop constant constituting the gain of the phase comparator 1, the gain of the charge pump circuit 2, the time constant of the low-pass filter 3, and the gain of the VCO 4. However, the increase of the loop constant causes an increase in jitter representing momentary swings of the output clock CK0. In the synchronization transfer period of the first conventional phase lock loop , the pull-in period is extremely large as compared to the lock-in period and occupies a major part of the synchronization transfer period accordingly.
The first conventional phase lock loop as described above has a disadvantage that the increase of the loop constant required for reduction of a synchronization transfer period causes an increase in jitter.
FIG. 3 shows a second conventional phase lock loop in a block diagram, in which constituent elements similar to those in FIG. 1 are designated by common reference numerals and in which the synchronization transfer period thereof is determined solely by a phase synchronization period. The second conventional phase lock loop has, in addition to a phase comparator 1, a charge pump circuit 2 and a low-pass filter which are similar to those in the first conventional phase lock loop, a variable delay circuit 40 for generating a delayed signal TD obtained by delaying the reference clock CKR based on the control signal CC, the variable delay circuit 40 being, for example, one of constituent elements of the VC0 4 in FIG. 2A.
In operation, after the reference clock CKR is supplied, the system functions similarly to the first conventional phase lock loop and transfers into a steady state such that the delayed signal TD, which is the output from the variable delay circuit 40, has a desired and predetermined small phase shift relative to the phase of the reference clock CKR.
The phase lock loop of FIG. 3 includes no frequency divider, so that the reference clock CKR and the output delayed signal TD have the same frequency. As a result of this, the frequency synchronization period, i.e., the pull-in period is not necessary. Namely, the synchronization transfer period is determined solely by a phase synchronization period, i.e., a lock-in period and is extremely small. However, in the absence of the frequency divider, the use of the phase lock loop is limited to the case wherein the frequency of the desired output clock CKO is same as the frequency of the reference clock CKR.